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K4S640832K K4S641632K
Synchronous DRAM
64Mb K-die SDRAM Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Revision History
Revision 0.0 0.1 0.2 0.3 1.0 1.1 Month January March April July September February Year 2005 2005 2005 2005 2005 2006 - Target spec release - Change DC current - Delete bit organization for x4 - Delete 7ns speed bin - Final spec release - Added 5ns speed bin for x16 History
Synchronous DRAM
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2M x 8Bit x 4Banks / 1M x 16Bit x 4Banks SDRAM
FEATURES
* JEDEC standard 3.3V power supply * LVTTL compatible with multiplexed address * Four banks operation * MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Burst read single-bit write operation * DQM (x8) & L(U)DQM (x16) for masking * Auto & self refresh * 64ms refresh period (4K cycle) * Pb/Pb-free Package * RoHS compliant for Pb-free Package
Synchronous DRAM
GENERAL DESCRIPTION
The K4S640832K / K4S641632K is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No. K4S640832K-T(U)C/L75 K4S641632K-T(U)C/L50 K4S641632K-T(U)C/L60 K4S641632K-T(U)C/L75 4Mb x 16 Orgainization 8Mb x 8 Max Freq. 133MHz(CL=3) 200MHz(CL=3) 166MHz(CL=3) 133MHz(CL=3) LVTTL 54pin TSOP(II) Pb (Pb-free) Interface Package
Organization 8Mx8 4Mx16
Row Address A0~A11 A0~A11
Column Address A0-A8 A0-A7
Row & Column address configuration
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Package Physical Dimension
Synchronous DRAM
0~8C 0.25 TYP 0.010 #54 #28 0.45~0.75 0.018~0.030 0.05 MIN 0.002 ( 0.50 ) 0.020
11.760.20 0.4630.008
#1 22.62 MAX 0.891 22.22 0.875 0.10 MAX 0.004 (
0.10 0.004
#27
0.21 0.008
0.05 0.002
1.00 0.039
0.10 0.004
0.71 ) 0.028
0.30 -0.05 0.012 +0.004 -0.002
+0.10
0.80 0.0315
54Pin TSOP(II) Package Dimension
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10.16 0.400 0.125+0.075 -0.035 0.005+0.003 -0.001 1.20 MAX 0.047
K4S640832K K4S641632K
FUNCTIONAL BLOCK DIAGRAM
Synchronous DRAM
I/O Control
LWE LDQM
Data Input Register Bank Select 2M x 8 / 1M x 16 Sense AMP 2M x 8 / 1M x 16 2M x 8 / 1M x 16 2M x 8 / 1M x 16 Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length Programming Register
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS Timing Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
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PIN CONFIGURATION (Top view) x8 x16
VDD VDD DQ0 DQ0 VDDQ VDDQ DQ1 N.C DQ2 DQ1 VSSQ VSSQ DQ3 N.C DQ4 DQ2 VDDQ VDDQ DQ5 N.C DQ6 DQ3 VSSQ VSSQ DQ7 N.C VDD VDD LDQM N.C WE WE CAS CAS RAS RAS CS CS BA0 BA0 BA1 BA1 A10/AP A10/AP A0 A0 A1 A1 A2 A2 A3 A3 VDD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Synchronous DRAM
x8
VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS
x16
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS
54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : (x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7) Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15) Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM DQ0 ~ N VDD/VSS VDDQ/VSSQ N.C/RFU
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS
Synchronous DRAM
Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Unit V V C W mA
Note : Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
Clock
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) Pin Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 4.0 5.0 5.0 6.5 Unit pF pF pF pF Note
RAS, CAS, WE, CS, CKE, DQM Address (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~DQ15)
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DC CHARACTERISTICS (x8)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C for x8) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Test Condition
Synchronous DRAM
Version 75 55 1 1 15
Unit
Note
ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS
mA mA
1
mA 6 3 3 30 mA 25 mA
Operating current (Burst mode) Refresh current Self refresh current
ICC4 ICC5 ICC6
80 85 1 400
mA mA mA uA
1 2 3 4
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S640832K-T(U)C 4. K4S640832K-T(U)L 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
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DC CHARACTERISTICS (x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C for x16 only) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L
Synchronous DRAM
Version
50 60 75
Unit
Note
ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS
80
70 1 1 15
55
mA mA
1
mA 6 3 3 30 mA 25 mA
Operating current (Burst mode) Refresh current Self refresh current
ICC4 ICC5 ICC6
110 110
100 100 1 400
85 85
mA mA mA uA
1 2 3 4
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S641632K-T(U)C 4. K4S641632K-T(U)L 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
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AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.3V
Synchronous DRAM
Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
Vtt = 1.4V
Unit V V ns V
1200 Output 870 30pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
30pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency = 3 CAS latency = 2 55 Version 50 10 15 15 40 60 12 18 18 42 100 60 2 2 CLK + tRP 1 1 1 2 1 65 75 15 20 20 45 Unit ns ns ns ns us ns CLK CLK CLK CLK ea 1, 6 2,5,6 5 2 2 3 4 Note 1 1 1 1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. 6. tRC =tRFC, tRDL = tWR.
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AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 Symbol 50 Min 5 2 2 2 1.5 1 1 Max 1000 4.5 4.5 Min 6 10 2.5 3 2.5 2.5 1.5 1 1 60 Max 1000 5 6 5 6
Synchronous DRAM
75 Min 7.5 10 3 3 2.5 2.5 1.5 0.8 1 Max 1000 5.4 6 5.4 6
Unit
Note
CLK cycle time CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z
tCC
ns
1
tSAC
ns
1,2
tOH tCH tCL tSS tSH tSLZ
ns ns ns ns ns ns ns
2 3 3 3, 4 3, 4 2
CAS latency=3 CAS latency=2
tSHZ
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. 4. tSS applies for address setup time, clock enable setup time, commend setup time and data setup time tSH applies for address holde time, clock enable hold time, commend hold time and data hold time
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter Output rise time Output fall time Output rise time Output fall time Symbol trh tfh trh tfh Condition Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Min 1.37 1.30 2.8 2.0 3.9 2.9 Typ Max 4.37 3.8 5.6 5.0 Unit Volts/ns Volts/ns Volts/ns Volts/ns Notes 3 3 1,2 1,2
Notes : 1. Rise time specification based on 0pF + 50 to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS.
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IBIS SPECIFICATION
IOH Characteristics (Pull-up)
Voltage (V) 3.45 3.30 3.00 2.70 2.50 1.95 1.80 1.65 1.50 1.40 1.00 0.20 200MHz/133MHz 200MHz/133MHz Min Max I (mA) I (mA) -1.68 -19.11 -0.35 -51.87 -3.75 -90.44 -6.65 -107.31 -13.75 -137.9 -17.75 -158.34 -20.55 -173.6 -23.55 -188.79 -26.2 -199.01 -36.25 -241.15 -46.5 -351.68 0 0 -100 -200 mA -300 -400 -500 -600 0.5
Synchronous DRAM
200MHz/133MHz Pull-up 1 1.5 2 2.5 3 3.5
Voltage
IOH Min (200MHz / 133MHz) IOH Max (200MHz / 133MHz)
200MHz/133MHz Pull-down
IOL Characteristics (Pull-down)
Voltage (V) 3.45 3.30 3.00 1.95 1.80 1.65 1.50 1.40 1.00 0.85 0.65 0.40 200MHz/133MHz 200MHz/133MHz Min Max I (mA) I (mA) 43.92 155.82 43.36 153.72 41.20 148.40 40.56 146.02 39.60 141.75 38.40 136.08 37.28 131.39 30.08 105.84 26.64 93.66 21.52 75.25 14.16 49.14
250
200
150 mA 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 Voltage
IOL Min (200MHz / 133MHz) IOL Max (200MHz / 133MHz)
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Synchronous DRAM
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 I (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31 20
Minimum VDD clamp current (Referenced to VDD)
15
mA
10
5
0 0 1 Voltage
I (mA)
2
3
Minimum VSS clamp current
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 I (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.0 0 -10 -20 mA -30 -40 -50 -60
-3
-2
-1
0
Voltage
I (mA)
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SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Self refresh Entry Exit
CKEn-1 CKEn CS RAS CAS WE
Synchronous DRAM
(V=Valid, X=Dont care, H=Logic high, L=Logic low)
DQM BA0,1 A10/AP A11, A9 ~ A0 Note
H H L H H H H
X H L H X X X X X L H L H
L L L H L L L L L H L X H L H L H L
L L H X L H H H L X V X X H X V X X H
L L H X H L L H H X V X X H X V X H
L H H X H H L L L X V X X H X V X H
X X X X X X X X X X X V X V V V
OP code X X Row address L H L H X L H X X
Column address Column address
1,2 3 3 3 3 4 4,5 4 4,5 6
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Clock suspend or active power down Bank selection All banks Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
H H L H L H H
X X V X X X 7
X
Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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